Your Logo Here
Total Concept Engineering --FPGA & CPLD DESIGN and IMPLEMENTATION


    At TCE we will work with you to review your FPGA/CPLD needs and requirements. Once these detailed requirements are documented we will translate them into Modular Verilog RTL code ready for testing. Test benches are developed using Modelsim to ensure that the RTL code meets the documented requirements. Both board level and chip level constraints are added and a place and route using vendor specific tools is preformed targeting a specific device. Working with the Board Level designer we will ensure that the optimal pin out is achieved thru floor‐planning to provide the best PCB layout possible. With 20 years of combine FPGA Hardware design and Board Integration Experience TCE is ready to help

FPGA Synthesis Tool

ModelSim Testbench