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Total Concept Engineering --Hardware Design Guides

Hardware Design Guides For On‐Die, and PCB level Power Distribution, SI & Timing

 

At TCE we offer customized Physical design guides that go beyond what you may receive from your typical silicon vendor. Often times the Silicon Vendor is unable to provide you a guide that provides you with the specific data that applies to your unique application. In addition you may find that there are significant gaps in the information provided. That is where TCE comes in. TCE takes a “leave no stone unturned” approach to design guide development. We use vendor supplied models, and Electrical Requirements, to construct a solution space that is customized to your application, but allows for easy adaptation to future use of the information on multiple projects and platforms.

 

On‐Die SSO Analysis for High Speed Serdes based ASIC’s

Illustration of HSS Cell's with adjacent IO cells, and Noise Plots
Illustration of HSS Cell's with adjacent IO cells, and Noise Plots

TCE ASIC Floor planning guides will provide you with the tools and information you need to have a correct by design chip level floor plan completed in one pass. No more wasted iterations, and guessing.